Sciweavers

69 search results - page 1 / 14
» Dynamic Fetch Engine for Simultaneous Multithreaded Processo...
Sort
View
APCSAC
2004
IEEE
13 years 8 months ago
Dynamic Fetch Engine for Simultaneous Multithreaded Processors
Abstract. While the fetch unit has been identified as one of the major bottlenecks of Simultaneous Multithreading architecture, several fetch schemes were proposed by prior works t...
Tzung-Rei Yang, Jong-Jiann Shieh
PARELEC
2006
IEEE
13 years 10 months ago
A Fault-Tolerant Dynamic Fetch Policy for SMT Processors in Multi-Bus Environments
Modern microprocessors get more and more susceptible to transient faults, e.g. caused by high-energetic particles due to high integration, clock frequencies, temperature and decre...
Bernhard Fechner
ISCA
1996
IEEE
102views Hardware» more  ISCA 1996»
13 years 8 months ago
Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor
Simultaneous multithreading is a technique that permits multiple independent threads to issue multiple instructions each cycle. In previous work we demonstrated the performance po...
Dean M. Tullsen, Susan J. Eggers, Joel S. Emer, He...
EUROMICRO
1998
IEEE
13 years 8 months ago
Data Speculative Multithreaded Architecture
In this paper we present a novel processor microarchitecture that relieves three of the most important bottlenecks of superscalar processors: the serialization imposed by true dep...
Pedro Marcuello, Antonio González
ARCS
2010
Springer
13 years 10 months ago
How to Enhance a Superscalar Processor to Provide Hard Real-Time Capable In-Order SMT
This paper describes how a superscalar in-order processor must be modified to support Simultaneous Multithreading (SMT) such that time-predictability is preserved for hard real-ti...
Jörg Mische, Irakli Guliashvili, Sascha Uhrig...