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JHSN
2000
112views more  JHSN 2000»
13 years 5 months ago
A hierarchical Quality of Service control architecture for configurable multimedia applications
In order to achieve the best application-level Quality-of-Service (QoS), multimedia applications need to be dynamically tuned and reconfigured to adapt to fluctuating computing an...
Baochun Li, William Kalter, Klara Nahrstedt
ISCA
2010
IEEE
222views Hardware» more  ISCA 2010»
13 years 8 months ago
Cohesion: a hybrid memory model for accelerators
Two broad classes of memory models are available today: models with hardware cache coherence, used in conventional chip multiprocessors, and models that rely upon software to mana...
John H. Kelm, Daniel R. Johnson, William Tuohy, St...
ACMMSP
2005
ACM
101views Hardware» more  ACMMSP 2005»
13 years 11 months ago
Transparent pointer compression for linked data structures
64-bit address spaces are increasingly important for modern applications, but they come at a price: pointers use twice as much memory, reducing the effective cache capacity and m...
Chris Lattner, Vikram S. Adve
IPPS
1999
IEEE
13 years 10 months ago
Non-Preemptive Scheduling of Real-Time Threads on Multi-Level-Context Architectures
The rapid progress in high-performance microprocessor design has made it di cult to adapt real-time scheduling results to new models of microprocessor hardware, thus leaving an un...
Jan Jonsson, Henrik Lönn, Kang G. Shin
ALGORITHMICA
2004
111views more  ALGORITHMICA 2004»
13 years 6 months ago
Non-Clairvoyant Scheduling for Minimizing Mean Slowdown
We consider the problem of scheduling dynamically arriving jobs in a non-clairvoyant setting, that is, when the size of a job in remains unknown until the job finishes execution. ...
Nikhil Bansal, Kedar Dhamdhere, Jochen Könema...