25 search results - page 4 / 5 » Dynamic hardware plugins in an FPGA with partial run-time re... |
ASAP
2007
IEEE
13 years 8 months ago
2007
IEEE
In this paper we present a novel adder/subtracter arithmetic unit that combines Binary and Binary Code Decimal (BCD) operations. The proposed unit uses effective addition/subtract...
FPT
2005
IEEE
13 years 10 months ago
2005
IEEE
SRAM FPGAs are vulnerable to security breaches such as bitstream cloning, reverse-engineering, and tampering. Bitstream encryption and authentication are two most effective and pr...
IPPS
2006
IEEE
13 years 10 months ago
2006
IEEE
Control algorithms implemented directly in hardware take advantage of parallel signal processing. Furthermore, implementing controller functionality in reconfigurable hardware fac...
CODES
2009
IEEE
13 years 8 months ago
2009
IEEE
Field-Programmable Gate Arrays (FPGAs) have become promising mapping fabric for the implementation of System-on-Chip (SoC) platforms, due to their large capacity and their enhance...
ERSA
2009
13 years 2 months ago
2009
In this paper, we introduce the Woolcano reconfigurable processor architecture. The architecture is based on the Xilinx Virtex-4 FX FPGA and leverages the Auxiliary Processing Uni...