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» Effective Exploitation of a Zero Overhead Loop Buffer
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LCTRTS
1999
Springer
13 years 9 months ago
Effective Exploitation of a Zero Overhead Loop Buffer
A Zero Overhead Loop Buffer (ZOLB) is an architectural feature that is commonly found in DSP processors. This buffer can be viewed as a compiler managed cache that contains a sequ...
Gang-Ryung Uh, Yuhong Wang, David B. Whalley, Sanj...
SC
2000
ACM
13 years 8 months ago
Hardware Prediction for Data Coherency of Scientific Codes on DSM
This paper proposes a hardware mechanism for reducing coherency overhead occurring in scientific computations within DSM systems. A first phase aims at detecting, in the address s...
Jean-Thomas Acquaviva, William Jalby
FPGA
2005
ACM
97views FPGA» more  FPGA 2005»
13 years 10 months ago
Techniques for synthesizing binaries to an advanced register/memory structure
Recent works demonstrate several benefits of synthesizing software binaries onto FPGA hardware, including incorporating hardware design into established software tool flows with m...
Greg Stitt, Zhi Guo, Walid A. Najjar, Frank Vahid
ESSOS
2010
Springer
13 years 10 months ago
BuBBle: A Javascript Engine Level Countermeasure against Heap-Spraying Attacks
Web browsers that support a safe language such as Javascript are becoming a platform of great interest for security attacks. One such attack is a heap-spraying attack: a new kind o...
Francesco Gadaleta, Yves Younan, Wouter Joosen
MICRO
2000
IEEE
176views Hardware» more  MICRO 2000»
13 years 4 months ago
An Advanced Optimizer for the IA-64 Architecture
level of abstraction, compared with the program representation for scalar optimizations. For example, loop unrolling and loop unrolland-jam transformations exploit the large regist...
Rakesh Krishnaiyer, Dattatraya Kulkarni, Daniel M....