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» Effective Software Self-Test Methodology for Processor Cores
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CODES
1999
IEEE
13 years 9 months ago
How standards will enable hardware/software co-design
o much higher levels of abstraction than today's design practices, which are usually at the level of synthesizable RTL for custom hardware or Instruction Set Simulator (ISS) f...
Mark Genoe, Christopher K. Lennard, Joachim Kunkel...
CODES
2001
IEEE
13 years 9 months ago
Hybrid global/local search strategies for dynamic voltage scaling in embedded multiprocessors
In this paper, we explore a hybrid global/local search optimization framework for dynamic voltage scaling in embedded multiprocessor systems. The problem is to find, for a multipr...
Neal K. Bambha, Shuvra S. Bhattacharyya, Jürg...
MICRO
2007
IEEE
168views Hardware» more  MICRO 2007»
13 years 11 months ago
Global Multi-Threaded Instruction Scheduling
Recently, the microprocessor industry has moved toward chip multiprocessor (CMP) designs as a means of utilizing the increasing transistor counts in the face of physical and micro...
Guilherme Ottoni, David I. August
BMCBI
2005
106views more  BMCBI 2005»
13 years 5 months ago
A multistep bioinformatic approach detects putative regulatory elements in gene promoters
Background: Searching for approximate patterns in large promoter sequences frequently produces an exceedingly high numbers of results. Our aim was to exploit biological knowledge ...
Stefania Bortoluzzi, Alessandro Coppe, Andrea Biso...
CC
2010
Springer
190views System Software» more  CC 2010»
14 years 5 days ago
Is Reuse Distance Applicable to Data Locality Analysis on Chip Multiprocessors?
On Chip Multiprocessors (CMP), it is common that multiple cores share certain levels of cache. The sharing increases the contention in cache and memory-to-chip bandwidth, further h...
Yunlian Jiang, Eddy Z. Zhang, Kai Tian, Xipeng She...