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LCTRTS
2007
Springer
13 years 12 months ago
Addressing instruction fetch bottlenecks by using an instruction register file
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
Stephen Roderick Hines, Gary S. Tyson, David B. Wh...
ISLPED
2010
ACM
169views Hardware» more  ISLPED 2010»
13 years 6 months ago
TurboTag: lookup filtering to reduce coherence directory power
On-chip coherence directories of today's multi-core systems are not energy efficient. Coherence directories dissipate a significant fraction of their power on unnecessary loo...
Pejman Lotfi-Kamran, Michael Ferdman, Daniel Crisa...
BC
2004
95views more  BC 2004»
13 years 5 months ago
Tactile efficiency of insect antennae with two hinge joints
Antennae are the main organs of the arthropod tactile sense. In contrast to other senses that are capable of retrieving spatial information, e.g. vision, spatial sampling of tactil...
André Frank Krause, Volker Dürr
ICPPW
2007
IEEE
14 years 2 days ago
Power Management of Multicore Multiple Voltage Embedded Systems by Task Scheduling
We study the role of task-level scheduling in power management on multicore multiple voltage embedded systems. Multicore on-achip, in particular DSP systems, can greatly improve p...
Gang Qu
PEWASUN
2006
ACM
13 years 11 months ago
Experimental analysis of a transport protocol for ad hoc networks (TPA)
Many previous papers have pointed out that TCP performance in multi-hop ad hoc networks is not optimal. This is due to several TCP design principles that reflect the characteristi...
Giuseppe Anastasi, Emilio Ancillotti, Marco Conti,...