5 search results - page 1 / 1 » Efficient BIST Hardware Insertion with Low Test Application ... |
DATE
1999
IEEE
13 years 8 months ago
1999
IEEE
In this paper, new and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis. The methodology is ba...
VLSID
2001
IEEE
14 years 4 months ago
2001
IEEE
In this paper, we propose a new transparent built-in self-test ( TBIST ) method to test multiple embedded memory arrays with various sizes in parallel. First, a new transparent tes...
ITC
1996
IEEE
13 years 8 months ago
1996
IEEE
Orthogonal scan paths, which follow the path of the data flow, can be used in data path designs to reduce the test overhead -- area, delay and test application time -- by sharing ...
ITC
2003
IEEE
13 years 9 months ago
2003
IEEE
This paper describes a Hybrid DFT (H-DFT) architecture for low-cost, high quality structural testing in the high volume manufacturing (HVM) environment. This structure efficiently...
DSD
2005
IEEE
13 years 10 months ago
2005
IEEE
The increasing amount of test data needed to test SOC (System-on-Chip) entails efficient design of the TAM (test access mechanism), which is used to transport test data inside the...