18 search results - page 1 / 4 » Efficient DSP algorithm development for FPGA and ASIC techno... |
VLSI
2007
Springer
13 years 11 months ago
2007
Springer
ERSA
2009
13 years 2 months ago
2009
Medium-grain reconfigurable hardware (MGRH) architectures represent a hybrid between the versatility of a field programmable gate array (FPGA) and the computational power of a cust...
ICMCS
2005
IEEE
13 years 10 months ago
2005
IEEE
The paper presents a high-performance architecture of the bit-plane coder for the embedded block coding algorithm in JPEG 2000. The architecture adopts a pipeline structure and is...
IPPS
2006
IEEE
13 years 11 months ago
2006
IEEE
The novel design of an efficient FPGA interconnection architecture with multiple Switch Boxes (SB) and hardwired connections for realizing data intensive applications (i.e. DSP ap...
ERSA
2006
13 years 6 months ago
2006
MIMO systems have attracted great attentions because of their huge capacity. The hardware implementation of MIMO decoder becomes a challenging task as the complexity of the MIMO sy...