69 search results - page 1 / 14 » Efficient Dynamic Scheduling Through Tag Elimination |
ISCA
2002
IEEE
13 years 9 months ago
2002
IEEE
An increasingly large portion of scheduler latency is derived from the monolithic content addressable memory (CAM) arrays accessed during instruction wakeup. The performance of th...
ICCD
2005
IEEE
14 years 1 months ago
2005
IEEE
The dynamic instruction scheduling logic is one of the most critical components of modern superscalar microprocessors, both from the delay and power dissipation standpoints. The d...
ITIIS
2010
12 years 11 months ago
2010
We propose a novel collision-avoidance algorithm for the active type RFID regarding an indoor tracking system. Several well-known collision avoidance algorithms are analyzed consi...
ICCD
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper presents a new scheduling technique to improve the speed, power, and scalability of a dynamic scheduler. In a high-performance superscalar processor, the instruction sc...
ISCAS
1999
IEEE
13 years 8 months ago
1999
IEEE
The energy usage of computer systems is becoming important, especially for portablebattery-operated applications and embedded systems. A significant reduction in the energy consum...