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TACO
2008
130views more  TACO 2008»
13 years 5 months ago
Efficient hardware code generation for FPGAs
r acceptance of FPGAs as a computing device requires a higher level of programming abstraction. ROCCC is an optimizing C to HDL compiler. We describe the code generation approach i...
Zhi Guo, Walid A. Najjar, Betul Buyukkurt
ICCAD
1999
IEEE
125views Hardware» more  ICCAD 1999»
13 years 9 months ago
Direct synthesis of timed asynchronous circuits
This paper presents a new method to synthesize timed asynchronous circuits directly from the specification without generating a state graph. The synthesis procedure begins with a ...
Sung Tae Jung, Chris J. Myers
FPGA
1995
ACM
142views FPGA» more  FPGA 1995»
13 years 9 months ago
The Design of RPM: An FPGA-based Multiprocessor Emulator
Recent advances in Field-Programmable Gate Arrays (FPGA) and programmable interconnects have made it possible to build efficient hardware emulation engines. In addition, improveme...
Koray Öner, Luiz André Barroso, Sasan ...
DAC
2003
ACM
14 years 6 months ago
Data communication estimation and reduction for reconfigurable systems
Widespread adoption of reconfigurable devices requires system level synthesis techniques to take an application written in a high level language and map it to the reconfigurable d...
Adam Kaplan, Philip Brisk, Ryan Kastner
SASP
2008
IEEE
77views Hardware» more  SASP 2008»
13 years 11 months ago
Resource Sharing in Custom Instruction Set Extensions
Abstract—Customised processor performance generally increases as additional custom instructions are added. However, performance is not the only metric that modern systems must ta...
Marcela Zuluaga, Nigel P. Topham