53 search results - page 1 / 11 » Efficient Interconnects for Clustered Microarchitectures |
IEEEPACT
2002
IEEE
13 years 9 months ago
2002
IEEE
Clustering is an effective microarchitectural technique for reducing the impact of wire delays, the complexity, and the power requirements of microprocessors. In this work, we inv...
CASES
2007
ACM
2007
ACM
INTACTE: an interconnect area, delay, and energy estimation tool for microarchitectural explorations
13 years 8 months ago
Prior work on modeling interconnects has focused on optimizing the wire and repeater design for trading off energy and delay, and is largely based on low level circuit parameters....
ASPDAC
2007
ACM
13 years 8 months ago
2007
ACM
- For modern processor designs in nanometer technologies, both block and interconnect pipelining are needed to achieve multi-gigahertz clock frequency, but previous approaches cons...
ISCA
2005
IEEE
13 years 10 months ago
2005
IEEE
One of the most important problems faced by microarchitecture designers is the poor scalability of some of the current solutions with increased clock frequencies and wider pipelin...
TCS
1998
13 years 4 months ago
1998
Recently a class of scalable multi-star optical networks is proposed in [2]. In this class of networks nodes are grouped into clusters. Each cluster employs a separate pair of bro...