2 search results - page 1 / 1 » Efficient Modeling and Floorplanning of Embedded-FPGA Fabric |
FPL
2007
Springer
13 years 10 months ago
2007
Springer
In this paper we present an automatic design flow for generating customized embedded FPGA (eFPGA) fabric and a domain specific SOC+eFPGA architecture. This design flow encompas...
ASPDAC
2006
ACM
13 years 10 months ago
2006
ACM
- Chip floorplan in a reticle for Multi-Project Wafer (MPW) plays a key role in deciding chip fabrication cost. In this paper1 , we propose a methodology to explore reticle floopla...