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» Efficient Rate Control for JPEG2000 Coder and Decoder
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VLSID
2003
IEEE
183views VLSI» more  VLSID 2003»
14 years 5 months ago
Design of a 2D DCT/IDCT application specific VLIW processor supporting scaled and sub-sampled blocks
We present an innovative design of an accurate, 2D DCT IDCT processor, which handles scaled and sub-sampled input blocks efficiently. In the IDCT mode, the latency of the processo...
Rohini Krishnan, Om Prakash Gangwal, Jos T. J. van...
TIP
2002
114views more  TIP 2002»
13 years 4 months ago
New architecture for dynamic frame-skipping transcoder
Abstract--Transcoding is a key technique for reducing the bitrate of a previously compressed video signal. A high transcoding ratio may result in an unacceptable picture quality wh...
Kai-Tat Fung, Yui-Lam Chan, Wan-Chi Siu