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ASPDAC
2007
ACM
158views Hardware» more  ASPDAC 2007»
13 years 10 months ago
Symbolic Model Checking of Analog/Mixed-Signal Circuits
This paper presents a Boolean based symbolic model checking algorithm for the verification of analog/mixedsignal (AMS) circuits. The systems are modeled in VHDL-AMS, a hardware des...
David Walter, Scott Little, Nicholas Seegmiller, C...
ICCD
2006
IEEE
125views Hardware» more  ICCD 2006»
14 years 3 months ago
Partial Functional Manipulation Based Wirelength Minimization
—In-place flipping of rectangular blocks/cells can potentially reduce the wirelength of a floorplan/placement solution without changing the chip area, In a recent work [Hao 05], ...
Avijit Dutta, David Z. Pan
BIRTHDAY
2008
Springer
13 years 8 months ago
AND/OR Multi-valued Decision Diagrams for Constraint Networks
The paper is an overview of a recently developed compilation data structure for graphical models, with specific application to constraint networks. The AND/OR Multi-Valued Decision...
Robert Mateescu, Rina Dechter
IJCAI
2001
13 years 7 months ago
Efficient Consequence Finding
We present an extensive experimental study of consequence-finding algorithms based on kernel resolution, using both a trie-based and a novel ZBDD-based implementation, which uses ...
Laurent Simon, Alvaro del Val
JUCS
2010
143views more  JUCS 2010»
13 years 4 months ago
Design of Arbiters and Allocators Based on Multi-Terminal BDDs
: Assigning one (more) shared resource(s) to several requesters is a function of arbiters (allocators). This class of decision-making modules can be implemented in a number of ways...
Václav Dvorák, Petr Mikusek