7 search results - page 2 / 2 » Efficient Runahead Execution: Power-Efficient Memory Latency... |
HPCA
2008
IEEE
14 years 5 months ago
2008
IEEE
The continued scaling of device dimensions and the operating voltage reduces the critical charge and thus natural noise tolerance level of transistors. As a result, circuits can p...
APCSAC
2000
IEEE
13 years 9 months ago
2000
IEEE
This paper briefly reviews the current research into RISC microprocessor architecture, which now seems to be so complex as to make the acronym somewhat of an oxymoron. In response...