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EUC
2004
Springer
13 years 8 months ago
Efficient Scheduling for Design Exploration with Imprecise Latency and Register Constraints
In archiectural synthesis, scheduling and resource allocation are important steps. During the early stage of the design, imprecise information is unavoidable. Under the imprecise ...
Chantana Chantrapornchai, Wanlop Surakumpolthorn, ...
DATE
2000
IEEE
88views Hardware» more  DATE 2000»
13 years 9 months ago
Techniques for Reducing Read Latency of Core Bus Wrappers
Today’s system-on-a-chip designs consist of many cores. To enable cores to be easily integrated into different systems, many propose creating cores with their internal logic sep...
Roman L. Lysecky, Frank Vahid, Tony Givargis
CORR
2007
Springer
154views Education» more  CORR 2007»
13 years 4 months ago
Application of a design space exploration tool to enhance interleaver generation
This paper presents a methodology to efficiently explore the design space of communication adapters. In most digital signal processing (DSP) applications, the overall performance ...
Cyrille Chavet, Philippe Coussy, Pascal Urard, Eri...