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VLSID
2005
IEEE
131views VLSI» more  VLSID 2005»
14 years 4 months ago
Efficient Space/Time Compression to Reduce Test Data Volume and Testing Time for IP Cores
Abstract-- We present two-dimensional (space/time) compression techniques that reduce test data volume and test application time for scan testing of intellectual property (IP) core...
Lei Li, Krishnendu Chakrabarty, Seiji Kajihara, Sh...
DATE
2002
IEEE
103views Hardware» more  DATE 2002»
13 years 9 months ago
Test Resource Partitioning and Reduced Pin-Count Testing Based on Test Data Compression
We present a new test resource partitioning (TRP) technique for reduced pin-count testing of system-on-a-chip (SOC). The proposed technique is based on test data compression and o...
Anshuman Chandra, Krishnendu Chakrabarty
TVLSI
2008
133views more  TVLSI 2008»
13 years 4 months ago
Test Data Compression Using Selective Encoding of Scan Slices
We present a selective encoding method that reduces test data volume and test application time for scan testing of Intellectual Property (IP) cores. This method encodes the slices ...
Zhanglei Wang, Krishnendu Chakrabarty
DATE
2002
IEEE
135views Hardware» more  DATE 2002»
13 years 9 months ago
Reducing Test Application Time Through Test Data Mutation Encoding
In this paper we propose a new compression algorithm geared to reduce the time needed to test scan-based designs. Our scheme compresses the test vector set by encoding the bits th...
Sherief Reda, Alex Orailoglu
DATE
2008
IEEE
126views Hardware» more  DATE 2008»
13 years 6 months ago
State Skip LFSRs: Bridging the Gap between Test Data Compression and Test Set Embedding for IP Cores
1 We present a new type of Linear Feedback Shift Registers, State Skip LFSRs. State Skip LFSRs are normal LFSRs with the addition of a small linear circuit, the State Skip circuit,...
V. Tenentes, Xrysovalantis Kavousianos, Emmanouil ...