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ACSD
2004
IEEE
113views Hardware» more  ACSD 2004»
13 years 9 months ago
Logic Synthesis for Asynchronous Circuits Based on Petri Net Unfoldings and Incremental SAT
The behaviour of asynchronous circuits is often described by Signal Transition Graphs (STGs), which are Petri nets whose transitions are interpreted as rising and falling edges of...
Victor Khomenko, Maciej Koutny, Alexandre Yakovlev
ARTS
1999
Springer
13 years 10 months ago
ProbVerus: Probabilistic Symbolic Model Checking
Model checking can tell us whether a system is correct; probabilistic model checking can also tell us whether a system is timely and reliable. Moreover, probabilistic model checkin...
Vicky Hartonas-Garmhausen, Sérgio Vale Agui...
ICCAD
2010
IEEE
124views Hardware» more  ICCAD 2010»
13 years 3 months ago
Symbolic performance analysis of elastic systems
Elastic systems, either synchronous or asynchronous, can be optimized for the average-case performance when they have units with early evaluation or variable latency. The performan...
Marc Galceran Oms, Jordi Cortadella, Michael Kishi...
LICS
2006
IEEE
13 years 11 months ago
Avoiding Determinization
Automata on infinite objects are extensively used in system specification, verification, and synthesis. While some applications of the automata-theoretic approach have been wel...
Orna Kupferman
SPIN
2010
Springer
13 years 4 months ago
Nevertrace Claims for Model Checking
In this paper, we propose the nevertrace claim, which is a new construct for specifying the correctness properties that either finite or infinite execution traces (i.e., sequence...
Zhe Chen, Gilles Motet