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DAC
2003
ACM
13 years 9 months ago
Efficient compression and application of deterministic patterns in a logic BIST architecture
We present a novel method to efficiently generate, compress and apply test patterns in a logic BIST architecture. Patterns are generated by a modified automatic test pattern gener...
Peter Wohl, John A. Waicukauski, Sanjay Patel, Min...
ITC
2000
IEEE
104views Hardware» more  ITC 2000»
13 years 8 months ago
Application of deterministic logic BIST on industrial circuits
We present the application of a deterministic logic BIST scheme on state-of-the-art industrial circuits. Experimental results show that complete fault coverage can be achieved for...
Gundolf Kiefer, Hans-Joachim Wunderlich, Harald P....
ET
2002
111views more  ET 2002»
13 years 3 months ago
Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST
In this paper a novel architecture for scan-based mixed mode BIST is presented. To reduce the storage requirements for the deterministic patterns it relies on a two-dimensional co...
Huaguo Liang, Sybille Hellebrand, Hans-Joachim Wun...
ETS
2006
IEEE
110views Hardware» more  ETS 2006»
13 years 9 months ago
Deterministic Logic BIST for Transition Fault Testing
BIST is an attractive approach to detect delay faults due to its inherent support for at-speed test. Deterministic logic BIST (DLBIST) is a technique which was successfully applie...
Valentin Gherman, Hans-Joachim Wunderlich, Jü...
VTS
2005
IEEE
96views Hardware» more  VTS 2005»
13 years 9 months ago
Implementing a Scheme for External Deterministic Self-Test
A new method for test resource partitioning is introduced which keeps the design-for-test logic independent of the test set and moves the test pattern dependent information to an ...
Abdul Wahid Hakmi, Hans-Joachim Wunderlich, Valent...