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» Efficient coupled noise estimation for on-chip interconnects
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DAC
1999
ACM
14 years 6 months ago
Noise-Aware Repeater Insertion and Wire-Sizing for On-Chip Interconnect Using Hierarchical Moment-Matching
Recently, several algorithms for interconnect optimization via repeater insertion and wire sizing have appeared based on the Elmore delay model. Using the Devgan noise metric [6] ...
Chung-Ping Chen, Noel Menezes
ICCD
1999
IEEE
99views Hardware» more  ICCD 1999»
13 years 9 months ago
Efficient Crosstalk Estimation
With the reducing distances between wires in deep submicron technologies, coupling capacitances are becoming significant as their magnitude becomes comparable to the area capacita...
Martin Kuhlmann, Sachin S. Sapatnekar, Keshab K. P...
DATE
2005
IEEE
100views Hardware» more  DATE 2005»
13 years 11 months ago
Modeling the Non-Linear Behavior of Library Cells for an Accurate Static Noise Analysis
In signal integrity analysis, the joint effect of propagated noise through library cells, and of the noise injected on a quiet net by neighboring switching nets through coupling c...
Cristiano Forzan, Davide Pandini
GLVLSI
2009
IEEE
172views VLSI» more  GLVLSI 2009»
13 years 9 months ago
Contact merging algorithm for efficient substrate noise analysis in large scale circuits
A methodology is proposed to efficiently estimate the substrate noise generated by large scale aggressor circuits. Small spatial voltage differences within the ground distribution...
Emre Salman, Renatas Jakushokas, Eby G. Friedman, ...