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DAC
2004
ACM
10 years 3 months ago
Efficient equivalence checking with partitions and hierarchical cut-points
Previous results show that both flat and hierarchical methodologies present obstacles to effectively completing combinational equivalence checking. A new approach that combines th...
Demos Anastasakis, Lisa McIlwain, Slawomir Pilarsk...
GLVLSI
2005
IEEE
97views VLSI» more  GLVLSI 2005»
9 years 8 months ago
On equivalence checking and logic synthesis of circuits with a common specification
In this paper we develop a theory of equivalence checking (EC) and logic synthesis of circuits with a common specification (CS). We show that two combinational circuits N1, N2 have...
Eugene Goldberg
ENTCS
2008
105views more  ENTCS 2008»
9 years 2 months ago
Checking Equivalence for Reo Networks
Constraint automata have been used as an operational model for component connectors described in the coordination language Reo which specifies the cooperation and communication of...
Tobias Blechmann, Christel Baier
VLSID
2001
IEEE
129views VLSI» more  VLSID 2001»
10 years 2 months ago
Design Of Provably Correct Storage Arrays
In this paper we describe a hardware design method for memory and register arrays that allows the application of formal equivalence checking for comparing a high-level register tr...
Rajiv V. Joshi, Wei Hwang, Andreas Kuehlmann
DAC
2002
ACM
10 years 3 months ago
HiPRIME: hierarchical and passivity reserved interconnect macromodeling engine for RLKC power delivery
This paper proposes a general hierarchical analysis methodology, HiPRIME, to efficiently analyze RLKC power delivery systems. After partitioning the circuits into blocks, we devel...
Yahong Cao, Yu-Min Lee, Tsung-Hao Chen, Charlie Ch...
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