7 search results - page 1 / 2 » Efficient equivalence checking with partitions and hierarchi... |
DAC
2004
ACM
14 years 5 months ago
2004
ACM
Previous results show that both flat and hierarchical methodologies present obstacles to effectively completing combinational equivalence checking. A new approach that combines th...
GLVLSI
2005
IEEE
13 years 10 months ago
2005
IEEE
In this paper we develop a theory of equivalence checking (EC) and logic synthesis of circuits with a common specification (CS). We show that two combinational circuits N1, N2 have...
ENTCS
2008
13 years 4 months ago
2008
Constraint automata have been used as an operational model for component connectors described in the coordination language Reo which specifies the cooperation and communication of...
VLSID
2001
IEEE
14 years 4 months ago
2001
IEEE
In this paper we describe a hardware design method for memory and register arrays that allows the application of formal equivalence checking for comparing a high-level register tr...
DAC
2002
ACM
14 years 5 months ago
2002
ACM
This paper proposes a general hierarchical analysis methodology, HiPRIME, to efficiently analyze RLKC power delivery systems. After partitioning the circuits into blocks, we devel...