4 search results - page 1 / 1 » Efficient mapping and voltage islanding technique for energy... |
SAC
2010
ACM
13 years 5 months ago
2010
ACM
Voltage islanding technique in Network-on-Chip (NoC) can significantly reduce the computational energy consumption by scaling down the voltage levels of the processing elements (P...
CODES
2007
IEEE
13 years 6 months ago
2007
IEEE
In this paper, we propose an efficient technique for run-time application mapping onto Network-on-Chip (NoC) platforms with multiple voltage levels. Our technique consists of a re...
TVLSI
2002
13 years 4 months ago
2002
The performance of many modern computer and communication systems is dictated by the latency of communication pipelines. At the same time, power/energy consumption is often another...
CASES
2003
ACM
2003
ACM
A hierarchical approach for energy efficient application design using heterogeneous embedded systems
13 years 8 months ago
Several features such as reconfiguration, voltage and frequency scaling, low-power operating states, duty-cycling, etc. are exploited for latency and energy efficient application ...