4 search results - page 1 / 1 » Efficient on-line interconnect testing in FPGAs with provabl... |
DATE
2006
IEEE
13 years 10 months ago
2006
IEEE
ITC
2003
IEEE
13 years 9 months ago
2003
IEEE
The interconnection network consumes the majority of die area in an FPGA. Presented is a scalable manufacturing test method for all SRAM-based FPGAs, able to detect multiple inter...
ITC
2002
IEEE
13 years 9 months ago
2002
IEEE
Conventional fault simulation techniques for FPGAs are very complicated and time consuming. The other alternative, FPGA fault emulation technique, is incomplete, and can be used o...
CODES
2010
IEEE
13 years 1 months ago
2010
IEEE
This paper presents an approach to system-level optimization of error detection implementation in the context of fault-tolerant realtime distributed embedded systems used for safe...