76 search results - page 1 / 16 » Efficient reachability checking using sequential SAT |
ASPDAC
2004
ACM
13 years 9 months ago
2004
ACM
Abstract
FMCAD
2004
Springer
13 years 10 months ago
2004
Springer
Most symbolic model checkers are based on either Binary Decision Diagrams (BDDs), which may grow exponentially large, or Satisfiability (SAT) solvers, whose time requirements rapi...
FMCAD
2004
Springer
13 years 9 months ago
2004
Springer
This work presents a memory-efficient All-SAT engine which, given a propositional formula over sets of important and non-important variables, returns the set of all the assignments...
ACSD
2003
IEEE
13 years 9 months ago
2003
IEEE
Abstract. The behaviour of asynchronous circuits is often described by Signal Transition Graphs (STGs), which are Petri nets whose transitions are interpreted as rising and falling...
PDPTA
2003
13 years 6 months ago
2003
We present a novel approach to parallel Boolean satisfiability (SAT) checking. A distinctive feature of our parallel SAT checker is that it incorporates all essential heuristics ...