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DAC
2004
ACM
14 years 4 months ago
Efficient timing closure without timing driven placement and routing
Miodrag Vujkovic, David Wadkins, William Swartz, C...
DAC
2009
ACM
14 years 4 months ago
A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion
As VLSI technology enters the nanoscale regime, interconnect delay has become the bottleneck of the circuit timing. As one of the most powerful techniques for interconnect optimiz...
Shiyan Hu, Zhuo Li, Charles J. Alpert
ICCAD
2004
IEEE
155views Hardware» more  ICCAD 2004»
14 years 16 days ago
A flexibility aware budgeting for hierarchical flow timing closure
—In this paper, we present a new block budgeting algorithm which speeds up timing closure in timing driven hierarchical flows. After a brief description of the addressed flow, ...
Olivier Omedes, Michel Robert, Mohammed Ramdani
ISPD
2010
ACM
217views Hardware» more  ISPD 2010»
13 years 10 months ago
ITOP: integrating timing optimization within placement
Timing-driven placement is a critical step in nanometerscale physical synthesis. To improve design timing on a global scale, net-weight based global timing-driven placement is a c...
Natarajan Viswanathan, Gi-Joon Nam, Jarrod A. Roy,...
VLSID
2002
IEEE
100views VLSI» more  VLSID 2002»
13 years 8 months ago
Layout-Driven Timing Optimization by Generalized De Morgan Transform
We propose a timing-oriented logic optimization technique called Generalized De Morgan (GDM) transform, that integrates gate resizing, net buffering and De Morgan transformation. ...
Supratik Chakraborty, Rajeev Murgai