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CLUSTER
2000
IEEE
13 years 9 months ago
Enabling High Performance Data Transfer on Cluster Architecture
In this article, we present some results on the communication performance of TCP/IP in a cluster of Pentium based workstations connected by a Gigabit Ethernet network. The experim...
Paul A. Farrell, Hong Ong, Stephen L. Scott
CLUSTER
2002
IEEE
13 years 9 months ago
Reliable Blast UDP: Predictable High Performance Bulk Data Transfer
High speed bulk data transfer is an important part of many data-intensive scientific applications. This paper describes an aggressive bulk data transfer scheme, called Reliable Bl...
Eric He, Jason Leigh, Oliver T. Yu, Thomas A. DeFa...
DAC
2001
ACM
14 years 5 months ago
Clustered VLIW Architectures with Predicated Switching
In order to meet the high throughput requirements of applications exhibiting high ILP, VLIW ASIPs may increasingly include large numbers of functional unitsFUs. Unfortunately, `sw...
Margarida F. Jacome, Gustavo de Veciana, Satish Pi...
IEEEPACT
2002
IEEE
13 years 9 months ago
Optimizing Loop Performance for Clustered VLIW Architectures
Modern embedded systems often require high degrees of instruction-level parallelism (ILP) within strict constraints on power consumption and chip cost. Unfortunately, a high-perfo...
Yi Qian, Steve Carr, Philip H. Sweany
DATE
2000
IEEE
139views Hardware» more  DATE 2000»
13 years 9 months ago
Target Architecture Oriented High-Level Synthesis for Multi-FPGA Based Emulation
This paper presents a new approach on combined highlevel synthesis and partitioning for FPGA-based multi-chip emulation systems. The goal is to synthesize a prototype with maximal...
Oliver Bringmann, Wolfgang Rosenstiel, Carsten Men...