11 search results - page 1 / 3 » Energy Benefits of a Configurable Line Size Cache for Embedd... |
ISVLSI
2003
IEEE
13 years 9 months ago
2003
IEEE
Previous work has shown that cache line sizes impact performance differently for different desktop programs – some programs work better with small line sizes, others with larger...
DAC
1999
ACM
14 years 5 months ago
1999
ACM
In embedded system design, the designer has to choose an onchip memory configuration that is suitable for a specific application. To aid in this design choice, we present a memory...
RSP
2003
IEEE
13 years 9 months ago
2003
IEEE
We describe cache architecture, intended for prototype-oriented IC platforms, that automatically finds the best cache configuration for a particular application. The cache itself ...
ICCD
2006
IEEE
14 years 1 months ago
2006
IEEE
— Traditional level-one instruction caches and data caches for embedded systems typically have the same capacities. Configurable caches either shut down a part of the cache to su...
ISVLSI
2008
IEEE
13 years 11 months ago
2008
IEEE
Active power used to be the primary contributor to total power dissipation of CMOS designs, but with the technology scaling, the share of leakage in total power consumption of dig...