5 search results - page 1 / 1 » Energy efficient application mapping to NoC processing eleme... |
NOCS
2009
IEEE
2009
IEEE
Energy efficient application mapping to NoC processing elements operating at multiple voltage levels
13 years 11 months ago
SOCC
2008
IEEE
13 years 11 months ago
2008
IEEE
— Scaling down the voltage levels of the processing elements (PEs) in a Network-on-Chip (NoC) can significantly reduce the computation energy consumption with an overhead of the...
SAC
2010
ACM
13 years 5 months ago
2010
ACM
Voltage islanding technique in Network-on-Chip (NoC) can significantly reduce the computational energy consumption by scaling down the voltage levels of the processing elements (P...
CODES
2007
IEEE
13 years 6 months ago
2007
IEEE
In this paper, we propose an efficient technique for run-time application mapping onto Network-on-Chip (NoC) platforms with multiple voltage levels. Our technique consists of a re...
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
With the increased use of embedded/portable devices such as smart cellular phones, pagers, PDAs, hand-held computers, and CD players, improving energy efficiency is becoming a cri...