Sciweavers

45 search results - page 9 / 9
» Energy efficient packet classification hardware accelerator
Sort
View
MICRO
2003
IEEE
128views Hardware» more  MICRO 2003»
13 years 10 months ago
IPStash: a Power-Efficient Memory Architecture for IP-lookup
Abstract—High-speed routers often use commodity, fully-associative, TCAMs (Ternary Content Addressable Memories) to perform packet classification and routing (IP lookup). We prop...
Stefanos Kaxiras, Georgios Keramidas
VISUALIZATION
2000
IEEE
13 years 9 months ago
FastSplats: optimized splatting on rectilinear grids
Splatting is widely applied in many areas, including volume, point-based, and image-based rendering. Improvements to splatting, such as eliminating popping and color bleeding, occ...
Jian Huang, Roger Crawfis, Naeem Shareef, Klaus Mu...
VVS
1996
IEEE
202views Visualization» more  VVS 1996»
13 years 9 months ago
Direct Volume Rendering with Shading via Three-Dimensional Textures
A new and easy-to-implement method for direct volume rendering that uses 3D texture maps for acceleration, and incorporates directional lighting, is described. The implementation,...
Allen Van Gelder, Kwansik Kim
TC
2008
13 years 4 months ago
DRES: Dynamic Range Encoding Scheme for TCAM Coprocessors
One of the most critical resource management issues in the use of ternary content addressable memory (TCAM) for packet classification/filtering is how to effectively support filte...
Hao Che, Zhijun Wang, Kai Zheng, Bin Liu
FCCM
2011
IEEE
241views VLSI» more  FCCM 2011»
12 years 8 months ago
Multilevel Granularity Parallelism Synthesis on FPGAs
— Recent progress in High-Level Synthesis (HLS) es has helped raise the abstraction level of FPGA programming. However implementation and performance evaluation of the HLS-genera...
Alexandros Papakonstantinou, Yun Liang, John A. St...