42 search results - page 1 / 9 » Energy optimization techniques in cluster interconnects |
ISLPED
2003
ACM
13 years 10 months ago
2003
ACM
× Ò Ò Ò Ö Ý¹ Æ ÒØ ÐÙ×Ø Ö× × Ö ÒØÐÝ ÓÑ Ò Ñ¹ ÔÓÖØ ÒØ ÓÒ ÖÒ ØÓ Ñ Ø × ×Ý×Ø Ñ× ÓÒÓÑ ÐÐÝ ØØÖ Ø Ú ÓÖ Ñ ÒÝ ÔÔÐ Ø ÓÒ...
CLUSTER
2007
IEEE
13 years 9 months ago
2007
IEEE
High-performance computing (HPC) systems consume a significant amount of power, resulting in high operational costs, reduced reliability, and wasting of natural resources. Therefor...
AC
2005
Springer
13 years 4 months ago
2005
Springer
Reducing power consumption has become a major challenge in the design and operation of today's computer systems. This chapter describes different techniques addressing this c...
CASES
2007
ACM
2007
ACM
INTACTE: an interconnect area, delay, and energy estimation tool for microarchitectural explorations
13 years 9 months ago
Prior work on modeling interconnects has focused on optimizing the wire and repeater design for trading off energy and delay, and is largely based on low level circuit parameters....
ISLPED
2005
ACM
13 years 10 months ago
2005
ACM
Network-on-chip (NoC) has been proposed as a solution for the global communication challenges of System-on-chip (SoC) design in the nanoscale technologies. NoC design with mesh ba...