5 search results - page 1 / 1 » Energy recovery for the design of high-speed, low-power stat... |
ISLPED
1996
ACM
13 years 8 months ago
1996
ACM
We present a low-power SRAM design based on the theory of energy recovery that reduces the dissipation associated with write operations while operating at high speed. The energy-r...
VLSID
2002
IEEE
14 years 4 months ago
2002
IEEE
Critical issues in designing a high speed, low power static RAM in deep submicron technologies are described along with the design techniques used to overcome them. With appropria...
GLVLSI
1999
IEEE
13 years 8 months ago
1999
IEEE
A novel low power and low transistor count static energy recovery full adder (SERF) is presented in this paper. The power consumption and general characteristics of the SERF adder...
MICRO
2003
IEEE
13 years 9 months ago
2003
IEEE
Energy-efficient processor design is becoming more and more important with technology scaling and with high performance requirements. Supply-voltage scaling is an efficient way to...
MICRO
1997
IEEE
13 years 8 months ago
1997
IEEE
Most modern microprocessors employ one or two levels of on-chip caches in order to improve performance. These caches are typically implemented with static RAM cells and often occu...