24 search results - page 2 / 5 » Energy-Effective Instruction Fetch Unit for Wide Issue Proce... |
IEEEPACT
2000
IEEE
13 years 9 months ago
2000
IEEE
In this paper, we look at two issues which could affect the performance of value prediction on wide-issue ILP processors. One is the large number of accesses to the value predicti...
MICRO
1994
IEEE
13 years 9 months ago
1994
IEEE
Multiple issue of instructions occurs in superscalar and VLIW machines. This paper investigates a third type of machine design, which combines the advantages of code compatibility...
ISCA
2000
IEEE
13 years 9 months ago
2000
IEEE
Our program benchmarks and simulations of novel circuits indicate that large-window processors are feasible. Using our redesigned superscalar components, a large-window processor ...
IEEEPACT
1999
IEEE
13 years 9 months ago
1999
IEEE
Trace cache, an instruction fetch technique that reduces taken branch penalties by storing and fetching program instructions in dynamic execution order, dramatically improves inst...
ACMMSP
2004
ACM
13 years 10 months ago
2004
ACM
As superscalar processors become increasingly wide, it is inevitable that the large set of instructions to be fetched every cycle will span multiple noncontiguous basic blocks. Th...