14 search results - page 1 / 3 » Energy-efficient redundant execution for chip multiprocessor... |
GLVLSI
2010
IEEE
13 years 4 months ago
2010
IEEE
Relentless CMOS scaling coupled with lower design tolerances is making ICs increasingly susceptible to wear-out related permanent faults and transient faults, necessitating on-chi...
DATE
2010
IEEE
13 years 9 months ago
2010
IEEE
EUC
2006
Springer
13 years 8 months ago
2006
Springer
Multicore processors promise higher throughput at lower power consumption than single core processors. Thus in the near future they will be widely used in hard real-time systems as...
PDP
2010
IEEE
13 years 8 months ago
2010
IEEE
In the last years high performance processor designs have evolved toward Chip-Multiprocessor (CMP) architectures that implement multiple processing cores on a single die. As the nu...
ISCA
2003
IEEE
13 years 9 months ago
2003
IEEE
To address the increasing susceptibility of commodity chip multiprocessors (CMPs) to transient faults, we propose Chiplevel Redundantly Threaded multiprocessor with Recovery (CRTR...