35 search results - page 1 / 7 » Enhancing Spatial Locality via Data Layout Optimizations |
EUROPAR
1998
Springer
13 years 9 months ago
1998
Springer
This paper aims to improve locality of references by suitably choosing array layouts. We use a new definition of spatial reuse vectors that takes into account memory layout of arra...
IEEEPACT
2009
IEEE
13 years 11 months ago
2009
IEEE
—With increasing numbers of cores, future CMPs (Chip Multi-Processors) are likely to have a tiled architecture with a portion of shared L2 cache on each tile and a bankinterleave...
ISCA
1999
IEEE
13 years 9 months ago
1999
IEEE
By optimizing data layout at run-time, we can potentially enhance the performance of caches by actively creating spatial locality, facilitating prefetching, and avoiding cache con...
TJS
2002
13 years 4 months ago
2002
A significant source for enhancing application performance and for reducing power consumption in embedded processor applications is to improve the usage of the memory hierarchy. In...
LCPC
1998
Springer
1998
Springer
A Loop Transformation Algorithm Based on Explicit Data Layout Representation for Optimizing Locality
13 years 9 months ago
We present a cache locality optimization technique that can optimize a loop nest even if the arrays referenced have different layouts in memory. Such a capability is required for a...