13 search results - page 1 / 3 » Error Diagnosis for Transistor-Level Verification |
DAC
1994
ACM
13 years 8 months ago
1994
ACM
This paper describes a diagnosis technique for locating design errors in circuit implementations which do not match their functional specification. The method efficiently propagat...
ENTCS
2007
13 years 4 months ago
2007
We describe techniques for diagnosing errors in formal equivalence checking of RTL and transistor level models of high performance microprocessors at Freescale Semiconductor Inc. ...
ITC
2003
IEEE
13 years 9 months ago
2003
IEEE
Test model generation is crucial in the test generation process of a high-performance design targeted for large volume production. A key process in test model generation requires ...
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
We present a complete top-down design of a low-power multi-channel clock recovery circuit based on gated current-controlled oscillators. The flow includes several tools and method...
DAC
2009
ACM
14 years 5 months ago
2009
ACM
Recent improvements in design verification strive to automate error detection and greatly enhance engineers' ability to detect functional errors. However, the process of diag...