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EUROMICRO
1999
IEEE
13 years 9 months ago
Error Recovery using Forced Validity Assisted by Executable Assertions for Error Detection: An Experimental Evaluation
This paper proposes and evaluates error detection and recovery mechanisms suitable for embedded systems. The purpose of these mechanisms is to provide detection of and recovery fr...
Martin Hiller
SIGSOFT
2008
ACM
14 years 5 months ago
Finding programming errors earlier by evaluating runtime monitors ahead-of-time
Runtime monitoring allows programmers to validate, for instance, the proper use of application interfaces. Given a property specification, a runtime monitor tracks appropriate run...
Eric Bodden, Patrick Lam, Laurie J. Hendren
DSN
2003
IEEE
13 years 10 months ago
Evaluation of Fault Handling of the Time-Triggered Architecture with Bus and Star Topology
Arbitrary faults of a single node in a time-triggered architecture (TTA) bus topology system may cause error propagation to correct nodes and may lead to inconsistent system state...
Astrit Ademaj, Håkan Sivencrona, Günthe...
ISCA
2012
IEEE
243views Hardware» more  ISCA 2012»
11 years 7 months ago
Lane decoupling for improving the timing-error resiliency of wide-SIMD architectures
A significant portion of the energy dissipated in modern integrated circuits is consumed by the overhead associated with timing guardbands that ensure reliable execution. Timing ...
Evgeni Krimer, Patrick Chiang, Mattan Erez
BMCBI
2007
122views more  BMCBI 2007»
13 years 4 months ago
TAP score: torsion angle propensity normalization applied to local protein structure evaluation
Background: Experimentally determined protein structures may contain errors and require validation. Conformational criteria based on the Ramachandran plot are mainly used to disti...
Silvio C. E. Tosatto, Roberto Battistutta