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ISPD
1998
ACM
91views Hardware» more  ISPD 1998»
13 years 9 months ago
Estimation of maximum current envelope for power bus analysis and design
In this paper we present an input pattern independent method to compute the maximum current envelope, which is an upper bound over all possible current waveforms drawn by a circui...
Sudhakar Bobba, Ibrahim N. Hajj
ASPDAC
2004
ACM
126views Hardware» more  ASPDAC 2004»
13 years 10 months ago
High-level area and power-up current estimation considering rich cell library
— Reducing the ever-growing leakage power is critical to power efficient designs. Leakage reduction techniques such as power-gating using sleep transistor insertion introduces la...
Fei Li, Lei He, Joseph M. Basile, Rakesh J. Patel,...
ICCAD
2000
IEEE
73views Hardware» more  ICCAD 2000»
13 years 9 months ago
Simulation and Optimization of the Power Distribution Network in VLSI Circuits
In this paper, we present simulation techniques to estimate the worst-case voltage variation using a RC model for the power distribution network. Pattern independent maximum envel...
Geng Bai, Sudhakar Bobba, Ibrahim N. Hajj
DAC
2006
ACM
14 years 5 months ago
Timing driven power gating
Power Gating is effective for reducing leakage power. Previously, a Distributed Sleep Transistor Network (DSTN) was proposed to reduce the sleep transistor area by connecting all ...
De-Shiuan Chiou, Shih-Hsin Chen, Shih-Chieh Chang,...