79 search results - page 1 / 16 » Evaluating Bufferless Flow Control for On-chip Networks |
NOCS
2010
IEEE
13 years 2 months ago
2010
IEEE
—With the emergence of on-chip networks, the power consumed by router buffers has become a primary concern. Bufferless flow control addresses this issue by removing router buffe...
MICRO
2010
IEEE
13 years 2 months ago
2010
IEEE
As the number of cores and threads in manycore compute accelerators such as Graphics Processing Units (GPU) increases, so does the importance of on-chip interconnection network des...
ICPP
2005
IEEE
13 years 9 months ago
2005
IEEE
In recent years integrating multiprocessors in a single chip is emerging for supporting various scientific and commercial applications, with diverse demands to the underlying on-c...
DSD
2006
IEEE
13 years 10 months ago
2006
IEEE
— An on-chip communication network is most power efficient when it operates just below the saturation point. For any given traffic load the network can be operated in this regi...
TVLSI
2008
13 years 4 months ago
2008
The on-chip communication architecture is a major determinant of overall performance in complex System-on-Chip (SoC) designs. Since the communication requirements of SoC components...