22 search results - page 1 / 5 » Evaluating design tradeoffs in on-chip power management for ... |
ISLPED
2007
ACM
13 years 6 months ago
2007
ACM
DSD
2006
IEEE
13 years 10 months ago
2006
IEEE
— An on-chip communication network is most power efficient when it operates just below the saturation point. For any given traffic load the network can be operated in this regi...
DATE
2003
IEEE
13 years 10 months ago
2003
IEEE
Interconnect networks play a critical role in shared memory multiprocessor systems-on-chip (MPSoC) designs. MPSoC performance and power consumption are greatly affected by the pac...
APPT
2009
Springer
13 years 8 months ago
2009
Springer
Abstract. In many-core CMP architectures, the cache coherence protocol is a key component since it can add requirements of area and power consumption to the final design and, there...
ASPLOS
2004
ACM
13 years 10 months ago
2004
ACM
Power density in high-performance processors continues to increase with technology generations as scaling of current, clock speed, and device density outpaces the downscaling of s...