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» Evaluation of Algorithms for Low Energy Mapping onto NoCs
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ISCAS
2007
IEEE
104views Hardware» more  ISCAS 2007»
13 years 10 months ago
Evaluation of Algorithms for Low Energy Mapping onto NoCs
—Systems on Chip (SoCs) congregate multiple modules and advanced interconnection schemes, such as networks on chip (NoCs). One relevant problem in SoC design is module mapping on...
César A. M. Marcon, Edson I. Moreno, Ney La...
SBCCI
2005
ACM
98views VLSI» more  SBCCI 2005»
13 years 10 months ago
Mapping embedded systems onto NoCs: the traffic effect on dynamic energy estimation
This work addresses the problem of application mapping in networks-on-chip (NoCs). It explores the importance of characterizing network traffic to effectively predict NoC energy c...
José Carlos S. Palma, César A. M. Ma...
VLSI
2005
Springer
13 years 10 months ago
Modeling the Traffic Effect for the Application Cores Mapping Problem onto NoCs
This work addresses the problem of application mapping in networks-on-chip (NoCs) having as goal to minimize the total dynamic energy consumption of a complex system-on-a-chip (So...
César A. M. Marcon, José Carlos S. P...
CODES
2007
IEEE
13 years 6 months ago
Incremental run-time application mapping for homogeneous NoCs with multiple voltage levels
In this paper, we propose an efficient technique for run-time application mapping onto Network-on-Chip (NoC) platforms with multiple voltage levels. Our technique consists of a re...
Chen-Ling Chou, Radu Marculescu
ISCAS
2005
IEEE
127views Hardware» more  ISCAS 2005»
13 years 10 months ago
Energy and latency evaluation of NoC topologies
Abstract — Mapping applications onto different networks-onchip (NoCs) topologies is done by mapping processing cores on local ports of routers considering requirements like laten...
Márcio Eduardo Kreutz, César A. M. M...