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DATE
2005
IEEE
113views Hardware» more  DATE 2005»
13 years 10 months ago
Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures
With new sophisticated compiler technology, it is possible to schedule distant instructions efficiently. As a consequence, the amount of exploitable instruction level parallelism...
Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda...
SAFECOMP
2007
Springer
13 years 11 months ago
Experimental Evaluation of the DECOS Fault-Tolerant Communication Layer
This paper presents an experimental evaluation of the fault-tolerant communication (FTCOM) layer of the DECOS integrated architecture. The FTCOM layer implements different agreemen...
Jonny Vinter, Henrik Eriksson, Astrit Ademaj, Bern...
HPCA
2008
IEEE
14 years 5 months ago
An OS-based alternative to full hardware coherence on tiled CMPs
The interconnect mechanisms (shared bus or crossbar) used in current chip-multiprocessors (CMPs) are expected to become a bottleneck that prevents these architectures from scaling...
Christian Fensch, Marcelo Cintra
IPPS
1999
IEEE
13 years 9 months ago
The Impact of Memory Hierarchies on Cluster Computing
Using off-the-shelf commodity workstations and PCs to build a cluster for parallel computing has become a common practice. A choice of a cost-effective cluster computing platform ...
Xing Du, Xiaodong Zhang
ICC
2007
IEEE
145views Communications» more  ICC 2007»
13 years 11 months ago
Click on a Cluster: A Viable Approach to Scale Software-Based Routers
—Extensible software-based routers running on commodity off-the-shelf hardware and open-source operating systems have been motivated by the progress in hardware technologies and ...
Qinghua Ye, Mike H. MacGregor