Sciweavers

11 search results - page 3 / 3
» Execution Latency Reduction via Variable Latency Pipeline an...
Sort
View
ICCD
2005
IEEE
159views Hardware» more  ICCD 2005»
13 years 10 months ago
Architectural-Level Fault Tolerant Computation in Nanoelectronic Processors
Nanoelectronic devices are expected to have extremely high and variable fault rates; thus future processor architectures based on these unreliable devices need to be built with fa...
Wenjing Rao, Alex Orailoglu, Ramesh Karri