453 search results - page 2 / 91 » Execution and Cache Performance of the Scheduled Dataflow Ar... |
ASAP
1997
IEEE
13 years 8 months ago
1997
IEEE
In this paper we present an approach for quantitative analysis of application-specific dataflow architectures. The approach allows the designer to rate design alternatives in a qu...
IPPS
2010
IEEE
13 years 2 months ago
2010
IEEE
Abstract--The now commonplace multi-core chips have introduced, by design, a deep hierarchy of memory and cache banks within parallel computers as a tradeoff between the user frien...
ASPLOS
2006
ACM
13 years 8 months ago
2006
ACM
This paper explores hierarchical instruction scheduling for a tiled processor. Our results show that at the top level of the hierarchy, a simple profile-driven algorithm effective...
DAC
2008
ACM
14 years 5 months ago
2008
ACM
Synchronous dataflow (SDF) has been successfully used in design tools for system-level simulation of wireless communication systems. Modern wireless communication standards involv...
SOCA
2010
IEEE
13 years 2 months ago
2010
IEEE
While modern CPUs offer an increasing number of cores with shared caches, prevailing execution engines for business processes, workflows, or Web service compositions have not been ...