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CSREAESA
2009
13 years 6 months ago
Built-In Self-Test of Embedded SEU Detection Cores in Virtex-4 and Virtex-5 FPGAs
A Built-In Self-Test (BIST) approach is presented for the Internal Configuration Access Port (ICAP) and Frame Error Correcting Code (ECC) logic cores embedded in Xilinx Virtex-4 an...
Bradley F. Dutton, Charles E. Stroud
FPL
2003
Springer
114views Hardware» more  FPL 2003»
13 years 10 months ago
Power Analysis of FPGAs: How Practical is the Attack?
Recent developments in information technologies made the secure transmission of digital data a critical design point. Large data flows have to be exchanged securely and involve en...
François-Xavier Standaert, Loïc van Ol...
ICSE
2008
IEEE-ACM
14 years 5 months ago
On the automation of fixing software bugs
Software Testing can take up to half of the resources of the development of new software. Although there has been a lot of work on automating the testing phase, fixing a bug after...
Andrea Arcuri
GECCO
2006
Springer
143views Optimization» more  GECCO 2006»
13 years 9 months ago
A hybridized genetic parallel programming based logic circuit synthesizer
Genetic Parallel Programming (GPP) is a novel Genetic Programming paradigm. Based on the GPP paradigm and a local search operator - FlowMap, a logic circuit synthesizing system in...
Wai Shing Lau, Kin-Hong Lee, Kwong-Sak Leung
DAC
2003
ACM
14 years 6 months ago
Using estimates from behavioral synthesis tools in compiler-directed design space exploration
This paper considers the role of performance and area estimates from behavioral synthesis in design space exploration. We have developed a compilation system that automatically ma...
Byoungro So, Pedro C. Diniz, Mary W. Hall