375 search results - page 1 / 75 » Explicit gate delay model for timing evaluation |
ISPD
2003
ACM
13 years 9 months ago
2003
ACM
Delay evaluation is always a crucial concern in the VLSI design and it becomes increasingly more critical in the nowadays deep-submicron technology. To obtain an accurate delay va...
ICCAD
2008
IEEE
14 years 1 months ago
2008
IEEE
Abstract— This paper presents an allocation method of decoupling capacitance that explicitly considers timing. We have found and focused that decap does not necessarily improve a...
ICCAD
2005
IEEE
14 years 1 months ago
2005
IEEE
Process variations in nanometer technologies are becoming an important issue for cutting-edge FPGAs with a multimillion gate capacity. Considering both die-to-die and withindie va...
ICCD
1993
IEEE
13 years 8 months ago
1993
IEEE
Ravel-XL is a single-boardhardware accelerator for gate-level digital logic simulation. It uses a standard levelizedcode approach to statically schedule gate evaluations.However, u...
VTS
2007
IEEE
13 years 10 months ago
2007
IEEE
: Conventionally, path delay tests are derived in a delay-independent manner, which causes most faults to be robustly untestable. Many non-robust tests are found but, in practice, ...