3 search results - page 1 / 1 » Exploiting DMA to enable non-blocking execution in Decoupled... |
IPPS
2009
IEEE
13 years 11 months ago
2009
IEEE
DTA (Decoupled Threaded Architecture) is designed to exploit fine/medium grained Thread Level Parallelism (TLP) by using a distributed hardware scheduling unit and relying on exi...
ISCAPDCS
2001
13 years 5 months ago
2001
This paper presents the evaluation of a non-blocking, decoupled memory/execution, multithreaded architecture known as the Scheduled Dataflow (SDF). The major recent trend in digit...
HPCA
2007
IEEE
14 years 4 months ago
2007
IEEE
Chip multiprocessors with multiple simpler cores are gaining popularity because they have the potential to drive future performance gains without exacerbating the problems of powe...