Sciweavers

4 search results - page 1 / 1
» Exploiting ILP, TLP and DLP with the Polymorphous TRIPS Arch...
Sort
View
ISCA
2003
IEEE
114views Hardware» more  ISCA 2003»
13 years 9 months ago
Exploiting ILP, TLP and DLP with the Polymorphous TRIPS Architecture
This paper describes the polymorphous TRIPS architecture which can be configured for different granularities and types of parallelism. TRIPS contains mechanisms that enable the p...
Karthikeyan Sankaralingam, Ramadass Nagarajan, Hai...
ACIVS
2005
Springer
13 years 10 months ago
Designing Area and Performance Constrained SIMD/VLIW Image Processing Architectures
Abstract. Image processing is widely used in many applications, including medical imaging, industrial manufacturing and security systems. In these applications, the size of the ima...
Hamed Fatemi, Henk Corporaal, Twan Basten, Richard...
CF
2009
ACM
13 years 11 months ago
Quantitative analysis of sequence alignment applications on multiprocessor architectures
The exponential growth of databases that contains biological information (such as protein and DNA data) demands great efforts to improve the performance of computational platforms...
Friman Sánchez, Alex Ramírez, Mateo ...
ICS
2007
Tsinghua U.
13 years 10 months ago
Tradeoff between data-, instruction-, and thread-level parallelism in stream processors
This paper explores the scalability of the Stream Processor architecture along the instruction-, data-, and thread-level parallelism dimensions. We develop detailed VLSI-cost and ...
Jung Ho Ahn, Mattan Erez, William J. Dally