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ATS
1997
IEEE
90views Hardware» more  ATS 1997»
13 years 10 months ago
Exploiting Logic Simulation to Improve Simulation-based Sequential ATPG
Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo,...
MTV
2007
IEEE
118views Hardware» more  MTV 2007»
14 years 21 hour ago
Reduction of Power Dissipation during Scan Testing by Test Vector Ordering
Test vector ordering is recognized as a simple and non-intrusive approach to assist test power reduction. Simulation based test vector ordering approach to minimize circuit transit...
Wang-Dauh Tseng, Lung-Jen Lee