10 search results - page 2 / 2 » Exploiting On-Chip Memory Bandwidth in the VIRAM Compiler |
ICASSP
2008
IEEE
14 years 7 days ago
2008
IEEE
Multiple memory banks design is employed in many high performance DSP processors. This architectural feature supports higher memory bandwidth by allowing multiple data memory acce...
PPOPP
2009
ACM
14 years 6 months ago
2009
ACM
On multiprocessors with explicitly managed memory hierarchies (EMM), software has the responsibility of moving data in and out of fast local memories. This task can be complex and...
HPCA
1998
IEEE
13 years 10 months ago
1998
IEEE
The performance of a concurrent multithreaded architectural model, called superthreading 15 , is studied in this paper. It tries to integrate optimizing compilation techniques and...
PDPTA
2000
13 years 7 months ago
2000
Exploiting compile time knowledge to improve memory bandwidth can produce noticeable improvements at run-time [13, 1]. Allocating the data structure [13] to separate memories when...
ASPLOS
2010
ACM
13 years 9 months ago
2010
ACM
This paper proposes an efficient hardware/software system that significantly enhances software security through diversified replication on multi-cores. Recent studies show that a ...