110 search results - page 1 / 22 » Exploiting Vector Parallelism in Software Pipelined Loops |
MICRO
2005
IEEE
13 years 10 months ago
2005
IEEE
An emerging trend in processor design is the addition of short vector instructions to general-purpose and embedded ISAs. Frequently, these extensions are employed using traditiona...
PLDI
2005
ACM
13 years 10 months ago
2005
ACM
Software pipelining of a multi-dimensional loop is an important optimization that overlaps the execution of successive outermost loop iterations to explore instruction-level paral...
CODES
2006
IEEE
13 years 10 months ago
2006
IEEE
Embedded processors have been increasingly exploiting hardware parallelism. Vector units, multiple processors or cores, hyper-threading, special-purpose accelerators such as DSPs ...
ASAP
2000
IEEE
13 years 8 months ago
2000
IEEE
Exploiting instruction-level parallelism (ILP) is extremely important for achieving high performance in application specific instruction set processors (ASIPs) and embedded proces...
IPPS
1998
IEEE
13 years 8 months ago
1998
IEEE
An effort to formalize the process of software pipelining loops with conditions is presented in this paper. A formal framework for scheduling such loops, based on representing set...